1. Field of the Invention
The invention relates to a semiconductor device and fabrication method thereof, and more particularly, to an approach of forming a two-layered hard mask on top of gate structure during self-aligned contact (SAC) process.
2. Description of the Prior Art
In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers.
In current fabrication of high-k metal gate transistors, two photo-etching processes are usually conducted to form contact plugs connecting gate structure and source/drain regions during self-aligned contacts (SAC) process. Since the hard mask above gate structure is typically composed of one single material, part of the hard mask is easily removed during formation of contact plugs so that contact plug connected to the gate structure would contact the contact plug connected to the source/drain region and results in short circuit. Hence how to improve this issue has become an important task in this field.